1. Field of the Invention:
The present invention relates to semiconductor devices of low and high voltage, vertically and laterally developed and to a combination of such devices on a single substrate. The present invention also relates to integrated injection logic combining low voltage devices, both laterally and vertically developed, which are in turn combined with high voltage devices, both laterally and vertically developed, with the latter, vertically developed devices, being associated, optimally, in a "Darlington" connection. The invention also relates to the method of making such combined devices.
2. Description of the Prior Art:
Vertically developed power transistors with the collectors down, and emitters up are conventional. Darlington connected power transistors, in which the collectors are formed lowermost, with the collectors sharing a common interconnecting region and common contacts are also conventional.
Such power devices are most commonly available in the NPN format using a substrate of N+ type material, upon which an N type epitaxial layer is formed. The NPN bases, of P material, are formed from the top, over the underlying N region, by a diffusing process. The NPN emitters are then formed over the bases. The final arrangement is a vertically developed transistor, having a first junction between collector and base and a second junction between base and emitter. Such vertical devices may be combined by a "Darlington" connection in which the emitter of one device is coupled to the base of the other device, and their collectors are connected together, by sharing the common, lower N region and a common substrate contact. It is also known that the devices may be conveniently driven by the addition of a laterally developed PNP transistor formed on the same substrate, which may be connected to the base of the "one" NPN.
Low voltage integrated injection logic (I.sup.2 L) has been described in the literature, as for instance Hart, C. M. and Slob, A., "Integrated Injection Logic--A New Approach to LSI", 1972 IEEE International Solid State Circuits Conference Proceedings, pp 92-93, and Berger, H. H. and Wiedman, S. K., "Merged Transistor Logic--A Low Cost Bipolar Logic Concept", 1972 ISSCC Proceedings, pp. 90-91. In addition, certain practical devices using the I.sup.2 L technique have been marketed by several semiconductor manufacturers.
The technique has several attractive features. One desirable feature of the technique is that the speed power product is very small, being demonstrated at less than 1.0 picojoules. In addition, because it can use conventional linear bipolar devices, the fabrication processes are conventional and manufacturing costs are relatively inexpensive.
The integrated injection logic, conventional integrated bipolar transistors are operated in an inverted mode. In I.sup.2 L logic, NPN transistors, which consist of successive horizontal layers have their emitter lowermost, the base above the emitter, and the collector topmost, usually in separate islands within the base. The resultant multiple collector device is compact and, when supplied with an appropriate base biasing current source or "injector", constitutes a basic "NOR" type gate, building block. The "NOR" function results when the collectors of different multiple collector devices are connected together. The current source used to bias the base of the I.sup.2 L multi-collector NPN transistors can be realized in many ways. The most popular I.sup.2 L configuration uses a lateral PNP transistor as the base biasing source. Another elementary I.sup.2 L function is that of simple inversion requiring a single collector, NPN and PNP base biasing source.